This invention relates generally to semiconductor devices, and more particularly to a flash memory device, especially NAND-type flash memory devices with page buffers.
A NAND type flash memory device generally includes a memory cell array, an x-decoder, a y-decoder, a high voltage circuit, a state machine circuit, an address register, a data register and sense amplifier circuit and an I/O register and buffer.
In the memory cell array of a typical NAND type flash memory device, memory cells are organized into memory cell strings. Each memory cell string includes a number of memory cells coupled in series. Generally, each memory cell string contains an equal number of memory cells for any given memory cell array. Thus, the memory cell strings serve as basic building blocks of the memory cell array in a typical NAND type flash memory device.
A number of memory cell strings are coupled in series to form a column. In each column, the memory cell strings are coupled to each other on a bit line. Each bit line is coupled to the data register and sense amplifier circuit. The data register and sense amplifier circuit includes a number of page buffers. One page buffer is coupled to each bit line and is used during read, program and verification operations of the memory cells which are coupled to each bit line.
The memory cell array is also organized into a number of rows, which are also called pages. Each page of memory cells includes an equal number of memory cells. The memory cells on each page are coupled together on a word line. A number of adjacent pages are organized into a memory cell block. Each memory cell block includes as many pages as there are memory cells in the memory cell string. Thus, each memory cell block includes a number of adjacent memory cell strings.
At a core of each memory cell is a floating gate that can be negatively charged with electrons. A charge status of the floating gate indicates whether the corresponding memory cell represents a logic high or a logic low. For example, if the floating gate is in a negatively charged state, the memory cell represents a logic low. If the floating gate is in a discharged state, the memory cell represents a logic high.
During a program operation, electrons are injected into the floating gates of memory cells that are currently in a discharged state but are desired to be in a negatively charged state. During an erase operation, electrons are removed from the floating gates of memory cells that are in a negatively charged state. Thus, a programmed memory cell represents a logic low while an erased memory cell represents a logic high. Generally, memory cells in one memory cell block are erased simultaneously during each erase operation while memory cells in each page are programmed simultaneously during each program operation.
After the memory cells are programmed or erased, they are verified to ensure that programming or erasing, respectively, has been performed correctly. In other words, in case of a program operation, the memory cells are checked during a program verification operation to determine if an adequate number of electrons have been injected into the floating gates of the programmed memory cells. In the case of the erase operation, the memory cells are checked during an erase verification operation to determine if electrons have been successfully removed from the floating gates of the erased memory cells.
During the program and erase verification operations, the page buffers in the data register and sense amplifier circuit are used to read and store the contents of memory cells. Since there is a page buffer associated with each bit line, an entire page is verified at a time during a program verification operation. A verification is performed for an entire erased memory cell block during the erase verification operation since memory cells of a memory cell block containing multiple pages are erased simultaneously.
During the program verification operation a voltage at a threshold voltage node in each page buffer is checked. The voltage at the threshold voltage node varies depending on the charge status of the memory cell whose content is being verified. If the memory cell has been programmed correctly, i.e., if the floating gate of the memory cell has been negatively charged properly, a threshold voltage is reached at the threshold voltage node. If the memory cell has not been programmed correctly, the threshold voltage is not reached.
Due to resistance of the memory cells, bit lines and the page buffers, the threshold voltage is not reached instantaneously even if the memory cell has been programmed correctly. Thus, if a program verification operation is performed too soon following a program operation, an erroneous conclusion that the memory cell has not been programmed properly may be reached. Thus, a set signal, which is activated after a pre-programmed delay, is generally used to initiate the program verification operation. The set signal with the programmed delay is typically generated by a timer sequence in the state machine circuit.
Using a set signal with a pre-programmed delay to initiate the program verification operation presents some difficulties. Since memory cells in different pages have different resistances from the page buffer to the memory cell and from the memory cell to a Vss voltage, a use of a uniform delay that has been pre-programmed for all the memory cells may present problems. Further, a time for the threshold node to reach the threshold voltage also depends on temperature, and it is not always possible to correctly estimate a required duration of the pre-programmed delay.
If the pre-programmed delay is too long, speed of the flash memory device is adversely affected because of an unnecessary additional waiting period. If the pre-programmed delay is too short, the program verification operation may be attempted before the threshold voltage is reached even if the memory cell that is being verified has been programmed correctly. In other words, if the program verification operation is performed too early, the verification may erroneously fail. If it is performed too late, an unnecessary additional delay may slow down the speed of the flash memory device.